Regviz

Cypress Semiconductor /psoc63 /USBFS0 /USBHOST /HOST_STATUS

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as HOST_STATUS

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Cypress Semiconductor/psoc63/USBFS0/USBHOST/HOST_STATUS#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CSTAT)CSTAT 0 (TMODE)TMODE 0 (SUSP)SUSP 0 (SOFBUSY)SOFBUSY 0 (URST)URST 0 (RSVD_5)RSVD_5 0 (RSTBUSY)RSTBUSY 0 (CLKSEL_ST)CLKSEL_ST 0 (HOST_ST)HOST_ST

Description

Host Status Register.

Fields

CSTAT

When this bit is ‘1’, it means that the device is connected. When this bit is ‘0’, it means that the device is disconnected. ‘0’ : Device is disconnected. ‘1’ : Device is connected. Notes:

  • This bit is initialized if the RST bit of the Host Control 1 Register (Host_CTL1) is set to ‘1’.
  • This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1).
TMODE

If this bit is ‘1’, it means that the device is connected in the full-speed mode. When this bit is ‘0’, it means that the device is connected in the low-speed mode. This bit is valid when the CSTAT bit of the Host Status Register (HOST_STATUS) is ‘1’. ‘0’ : Low-speed. ‘1’ : Full-speed. Notes:

  • This bit is initialized if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to ‘1’.
  • This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1).
SUSP

If this bit is set to ‘1’, the USB Host is placed into the suspend state. If this bit is set to ‘0’ while it is ‘1’ or the USB bus is placed into the k-state mode, the suspend state is released, and the RWIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to ‘1’. Set to ‘1’ : Suspend. Set ‘0’ while this bit is ‘1’ : Resume. Others : Holds the status. Notes:

  • This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to ‘1’.
  • This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1).
  • If this bit is set to ‘1’, this bit must not be set to ‘1’ until the RWIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to ‘1’.
  • Do not set this bit to ‘1’ while the USB is active (during USB bus resetting, data transfer, or SOF timer running).
  • If the value of this bit is changed, it is not immediately reflected on the state of the USB bus. To check whether or not the state is updated, read this bit.
SOFBUSY

When a SOF token is sent using the Host Token Endpoint Register (HOST_TOKEN), this bit is set to ‘1’, which means that the SOF timer is active. When this bit is ‘0’, it means that the SOF timer is under suspension. To stop the active SOF timer, write ‘0’ to this bit. However, if this bit is written with ‘1’, its value is ignored. ‘0’ : The SOF timer is stopped. ‘1’ : The SOF timer is active. Notes:

  • This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to ‘1’.
  • This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1).
  • The SOF timer does not stop immediately after this bit has been set to ‘0’ to stop the SOF timer. To check whether or not the SOF timer is stopped, read this bit.
URST

When this bit is set to ‘1’, the USB bus is reset. This bit continues set to ‘1’ during USB bus resetting, and changes to ‘0’ when USB bus resetting is ended. If this bit is set to ‘0’, no processing is performed.
RSVD_5

N/A
RSTBUSY

This bit shows that USB Host is being reset internally. If the RST bit of the Host Control 1 Register (HOST_CTL1) is set to ‘1’, this bit is set to ‘1’. If the RST bit of Host Control 1 Register (HOST_CTL1) is set to ‘0’, this bit is set to ‘0’. ‘0’ : USB Host isn’t being reset. ‘1’ : USB Host is being reset. Notes:

  • If this bit is ‘1’, the token must’t be executed.
  • This bit isn’t set to ‘0’ or ‘1’ immediately evne if the RST bit of Host Control 1 Register (HOST_CTL1) is set to ‘0’ or ‘1’.
CLKSEL_ST

This bit shows whether it is full-speed or not. If the CLKSEL bit of the Host Control 1 Register (HOST_CTL1) is set to ‘1’, this bit is set to ‘1’. ‘0’ : Low speed ‘1’ : Full speed Note:

  • If this bit is different from the CLKSEL bit, The execution of the token and bus reset must be waited until the match.
  • This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1).
HOST_ST

This bit shows whether it is USB Host mode. If the HOST bit of the Host Control Register (HOST_CTL0) is set to ‘1’, this bit is set to ‘1’. ‘0’ : USB Device ‘1’ : USB Host Notes:

  • If this bit is different from the CLKSEL bit, The execution of the token must be waited until the match.
  • This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1).

Links

()

Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data